1. Field of the Invention
This invention is related to the field of processors and, more particularly, to issue and retirement mechanisms in processors.
2. Description of the Related Art
Processors typically execute instructions in one or more pipelines. A first pipeline stage, referred to as the issue stage, is the stage at which a given instruction selected for issue. A second pipeline stage, referred to as the retirement stage or the graduation stage, is the stage at which the instruction commits its results to architected state. The retirement/graduation stage may also be that stage at which an instruction reports any exceptions that may have been experienced during execution, or a different stage may be used for this purpose.
To support precise exceptions: (i) the instructions prior to an instruction experiencing an exception update architected state prior to the exception occurring; and (ii) instructions subsequent to the instruction experiencing the exception do not update architected state prior to the exception occurring. If various pipelines in a processor have different lengths between issue and exception reporting or retirement/graduation, a mechanism is needed to ensure that precise exceptions are supported (assuming the architecture being implemented by the processor includes precise exceptions).